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I've been using Makefile and to keep some stuff sepparate I decided to include a new common makefile. The problem I faced is that my First makefile looks like this:
Filename Makefile.test
include ./Makefile.a
all: a b c
@echo "b"
@echo "c"
Filename Makefile.a
@echo "a"
When I execute my makefile: make -f Makefile.test I only get "a" printed out and it finishes.
The only way to make it work is place the include bellow (anywhere) the all: target
Is there a reason why this behaves liks this?
Thanks!
make just pulls Makefile.a into the current Makefile in the same way that #include <x.h> does in C: it inserts the contents of Makefile.a to replace the include statement and keeps going. The result is that make sees this when it starts figuring out what to do:
@echo "a"
all: a b c
@echo "b"
@echo "c"
So the first target in source-order will be a and since you didn't specify a target, make will use the first one. That's where your result comes from.
You could explicitly specify the all target if you wanted:
make -f Makefile.test all
That would use the all target regardless of where it appears in the Makefile.
If you're using GNU Make, then you could use .DEFAULT_GOAL to specify a default target inside Makefile.test and then you wouldn't have to worry about the order:
include ./Makefile.a
all: a b c
@echo "b"
@echo "c"
.DEFAULT_GOAL := all
Thanks to Idelic for the reminder about this.
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