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What is "concurrent assignment to a non-net <port_name> is not permitted" Verilog simulation error?

This is my cpu design code, which contains a series of ports. Only clk is a input:

module cpu_1(clk, inst_out, m1_out, QA, QB, IMME, WREG, M2REG, WMEM, ALUIMM, REGR1, m1_select, ALUC);
  input clk;
  output wire [31:0]inst_out;
  wire [31:0]ifid_out;
  output wire [3:0]ALUC;
  output wire [4:0]m1_out;
  output wire [31:0]QA;
  output wire [31:0]QB;
  output wire [31:0]IMME;
  output wire WREG, M2REG, WMEM, ALUIMM, REGR1, m1_select;
  wire [5:0]OP;
  wire [4:0]RS;
  wire [4:0]RT;
  wire [4:0]RD;
  wire [4:0]SA;
  wire [5:0]FUNC;
  wire [15:0]IMM;
  assign OP=ifid_out[31:26];
  assign RS=ifid_out[25:21];
  assign RT=ifid_out[20:16];
  assign RD=ifid_out[15:11];
  assign SA=ifid_out[10:6];
  assign FUNC=ifid_out[5:0];
  assign IMM=ifid_out[15:0];
  multiplexer_add4 ma4(pc_out, pc_in);
  program_counter pc(pc_in, pc_out);
  instruction_file INST_FILE(pc_out, inst_out);
  if_id IF_ID(inst_out, ifid_out, clk);
  control_unit CTRL(OP, FUNC, WREG, M2REG, WMEM, ALUC, ALUIMM, REGR1);
  multiplexer_1 m1(m1_select, RD, RT, m1_out);
  register_file rf(RS, RT, QA, QB);
  multiplexer_extension me(IMM, IMME);
  id_exe ID_EXE(WREG, M2REG, WMEM, ALUC, ALUIMM, m1_out, QA, QB, IMME, clk);
endmodule
This is part of my cpu testbench code. I want to instantiate the cpu module:
module cpu_1_tb;
reg clk;
reg [31:0]inst_out;
reg [4:0]m1_out;
reg [31:0]QA;
reg [31:0]QB;
reg [3:0]ALUC;    
reg [31:0]IMME;
reg WREG, M2REG, WMEM, ALUIMM, REGR1, m1_select;
cpu_1 cpu_1_instance
.clk(clk),
.inst_out(inst_out),
.m1_out(m1_out),
.QA(QA),
.QB(QB),
.ALUC(ALUC),
.IMME(IMME),
.WREG(WREG),
.M2REG(M2REG),
.WMEM(WMEM),
.ALUIMM(ALUIMM),
.REGR1(REGR1),
.m1_select(m1_select)
However I encounter this error. What is the cause of the error and what can I do to solve it?
You should not connect a module output signal to a reg in your testbench.  Your tool considers a reg to be a "non-net".
In your testbench, change:
reg [31:0]inst_out;
wire [31:0]inst_out;
You should do the same for any other outputs.
        
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